This lesson is optional background, not a section of the HAT-1 paper. HAT-1 tests verbal, analytical and quantitative reasoning only; the orientation lesson is explicit that there is no technical section. Digital logic is included because it sits directly beneath the number systems and programming you have just covered: gates are what add binary numbers, and Boolean expressions are what conditions in code compile down to. For computing, electronics and electrical candidates it is the most likely place for a short, self-contained numerical question on a technical course.
It is also the fairest topic of its kind. Logic has no interpretation, no vocabulary and no estimation. Given the inputs and the gate, there is exactly one output, and given the truth table, exactly one answer — which means these marks depend only on knowing five gate definitions and two laws.
Two identities do most of the work in expression questions; meet them before the procedure uses them.
Work in truth tables for circuit questions and with those two identities for expression questions.
Writing a column per gate is why these questions are reliable. Every column depends only on the columns to its left, so there is no point at which you are holding intermediate results in your head, and any error is visible on the page.
Truth tables for the five gates. The output is a 1 only in the row where the gate's condition is satisfied.
| A | B | AND | OR | NAND | NOR | XOR |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 |
AND outputs a 1 only when both inputs are 1. OR outputs a 1 when at least one input is 1. NOT inverts a single input. NAND and NOR are the negations of AND and OR, so their columns are simply inverted. XOR, the exclusive OR, outputs a 1 when the inputs differ — and that is the column worth memorising separately, because it is the one used in addition.
De Morgan's laws convert between AND and OR under negation. They are the most commonly tested identities in the whole topic.
Read them as a rule rather than a formula: negate each input, and the gate flips. This is exactly what a compiler does when it rewrites a condition such as "if not (x > 0 and y > 0)" into "if x ≤ 0 or y ≤ 0", which is why the law shows up in programming as well as in circuit questions.
Useful simplifications. A AND 0 is 0, A AND 1 is A, A OR 0 is A, A OR 1 is 1, A OR (NOT A) is 1, A AND (NOT A) is 0, and A OR (A AND B) is A. This last one, absorption, looks like it should be more complicated than it is: if A is true the whole expression is true regardless of B, and if A is false both terms are false.
NAND and NOR are universal gates. Either one alone can build every other gate, so a single gate type suffices to construct any circuit. Questions often ask which gate is universal, and both NAND and NOR are correct answers to that wording.
Addition is the standard application. The half adder takes two single bits and produces a sum and a carry.
The sum bit is 1 when the two bits differ, which is exactly XOR, and the carry is 1 only when both are 1, which is AND. A full adder handles a carry coming in as well, and is built from two half adders combined with an OR gate — which is how the whole chain from gates to arithmetic is closed.
Build the truth table for Y = (A AND B) OR (NOT C), then simplify if you can.
Three inputs, eight rows. Evaluate the inner AND first (column AB), then NOT C, then the final OR:
A B C | AB | !C | Y = AB OR !C 0 0 0 | 0 | 1 | 1 0 0 1 | 0 | 0 | 0 0 1 0 | 0 | 1 | 1 0 1 1 | 0 | 0 | 0 1 0 0 | 0 | 1 | 1 1 0 1 | 0 | 0 | 0 1 1 0 | 1 | 1 | 1 1 1 1 | 1 | 0 | 1
Read the final column: Y is 0 only when C is 1 and the pair (A, B) is not both 1 — three of the eight rows. No single-gate form captures that pattern, so the table itself is the simplified answer.
Now simplify an expression instead: Y = A AND (NOT A OR B). Distribute the AND over the OR: Y = (A AND NOT A) OR (A AND B). The first term is 0, because a value cannot be both true and false. So Y = 0 OR (A AND B), which is A AND B.
The truth table confirms it in four rows. With A = 0 the whole expression is 0 immediately, whatever B is, because the outer gate is AND. With A = 1 the bracket becomes 0 OR B, which is just B, so the output equals B. So the output is 1 only when A is 1 and B is 1 — which is exactly A AND B. Two methods, one answer: if the algebra is not coming, four rows always work.
When does an XOR gate output a 1?
Apply De Morgan's law to NOT(A AND B).
In a half adder, which gate produces the carry output?
Without looking back: state both of De Morgan's laws, and give the two outputs of a half adder in terms of the input bits.
The answer is: NOT(A AND B) equals (NOT A) OR (NOT B), and NOT(A OR B) equals (NOT A) AND (NOT B); the sum is A XOR B and the carry is A AND B.
Fill in the blanks from memory:
A gate that can be used to build every other gate is called a gate, and both NAND and qualify. In a half adder the sum bit is produced by an gate.
Build the truth table for a full adder: inputs A, B and a carry-in C, with a sum output and a carry-out output. Then verify one row by hand arithmetic.
Three inputs give eight rows. For each row, work the first half adder on A and B to get s1 and c1, then the second half adder on s1 and C to get the final sum and c2, and finally OR the two carries, since a carry can arrive from either stage.
The check row: A = 1, B = 1, C = 1. In binary, 1 + 1 + 1 is 3, which is 11 in binary, so the sum bit is 1 and the carry-out is 1. Confirm your table gives the same. If it gives 0 and 1 instead, the second half adder was applied to the wrong intermediate value.
Then answer the question the whole module has been building towards: how many full adders are needed to add two eight-bit numbers? Eight, one per bit position, with the carry from each stage feeding the next, and the carry-out of the last stage becoming a ninth bit of the result. Gates become arithmetic, arithmetic becomes a processor, and every step of it is the same handful of definitions you just used.
That completes the optional engineering background, and the course. You now have the test format, a weightage-based study plan, the arithmetic and reasoning techniques, the verbal question types, and the accuracy habits that support them. The last thing worth doing is a full timed mock under the pacing rules from Module 1, because the paper tests recall under a clock, and the clock is the part no amount of reading can prepare you for.