No Flags Register, No Condition Codes, No CMOV

Three targets, one C function, three DISJOINT sets

Now the comparison that the whole section exists for. One source file, three --target= flags, one compiler, one optimisation level — so a row that disagrees with another row is a difference between the targets and not between the bodies of work someone typed. IT IS NOT A TIMING AND NOT A SPEEDUP, and there is no ratio anywhere in this table.

$ python3 rvabi.py --run | sed -n '/the mnemonics in the corpus/,+3p'
  target  the mnemonics in the corpus            the idiom they are        total
  riscv64  blt(6), bge(4), c.beqz(5), c.bnez(1), bne(1)   branches          17
  aarch64  csel(14), cneg(2)                     conditional moves / sets 16
  x86-64   cmovel(3), cmoveq(3), cmovgel(1),
           cmovgl(3), cmovll(4), cmovsl(2)        conditional moves        16

  THE THREE SETS, DISJOINT -- computed, and printed whatever they
  turn out to be:
    riscv64  n x86-64   = EMPTY
    aarch64  n riscv64  = EMPTY
    aarch64  n x86-64   = EMPTY
    union of the three = 13 distinct mnemonics; sum of the sets = 13
    and every set is non-empty: aarch64=2, riscv64=5, x86-64=6
                

Union is 13, sum of the three sets is 13, so nothing is in two sets. The disjointness is computed, and printed whether or not it is empty, because the first version of this section wrote the word “disjoint” in a paragraph and never computed an intersection — which is the difference between a claim and a measurement, and the same failure shape as the zero-disagreement cross-check.

And note the shape of each set. RISC-V’s five are all branches. AArch64’s two are csel and cneg. x86-64’s are six cmov spellings — six rather than one because cmovll is the 32-bit “less” form and cmovll is not cmovl, and there are sixteen conditions times two operand sizes. A reader who wants to see that table is better served by a prefix match than by sixteen enumerated spellings, and the artifact matches on the prefix for a reason it documents: an enumerated table goes quietly empty the first time one is missed, and an empty table reads as “this target has no conditional move”, which is the one conclusion it must never support.

The three idioms, instruction by instruction

$ python3 rvabi.py --run | sed -n '/THE THREE IDIOMS SIDE BY SIDE/,+4p'
    mymin    a < b ? a : b
      riscv64 : blt        a0, a1, 0x10 | c.mv         a0, a1 | c.jr         ra
      aarch64 : cmp   w0, w1    | csel  w0, w0, w1, lt | ret
      x86-64  : movl  %esi, %eax | cmpl  %esi, %edi | cmovll %edi, %eax | retq

        the idiom: riscv64 branch | aarch64 csel | x86-64 cmov
                

Three architectures, one C function, one compiler — and the arithmetic is not a cost either. On x86-64 the sequence for mymin is mov / cmp / cmov / ret: four instructions where RISC-V’s is three. And the reason is not that x86-64 is worse at selects:

• x86-64 needs the mov because the candidate value has to be in the register the cmov will write, and it is not there yet.
• AArch64 needs the cmp because NZCV has to be set before csel can read it.
• RISC-V needs neither, because blt compares two registers as part of the branch and there is nothing to set up.

So the absence of a flags register is not uniformly a cost. It costs the compiler a CMOVcc to reach for, and it saves the mov and the cmp that CMOVcc depends on.WHICH OF THOSE WINS ON REAL HARDWARE IS NOT MEASURABLE HERE AND IS NOT CLAIMED — there is no RISC-V machine, no AArch64 machine, and no cycle measured anywhere in this course.

Why csel has a fourth operand at all

“csel exists because NZCV exists” is only worth something if csel really is an instruction that reads a condition, and the condition is a four-bit field. The artifact decodes the AArch64 words with the AArch64 course’s own a64dec.py — a second decoder, from a different course, and neither it nor rvdec.py is a disassembler:

$ python3 rvabi.py --run | sed -n '/word.*the reader says/,+3p'
  word        the reader says  the decoder says         condition field
  0x5a805400  cneg             cneg     w0, w0, mi   bits[15:12] = 0x5   cond 5
  0x1a81b000  csel             csel     w0, w0, w1, lt bits[15:12] = 0xb  cond 11
                

And here is the out-of-encodings argument, counted rather than asserted. A conditional move needs three registers — two candidates and a destination — and the I-type format has three register fields: rd at bits[9:7], rn at bits[19:15], rm at bits[4:0]. A 64-bit I-type instruction is 32 bits: 7 of opcode, 3 of funct3, 15 of register, and 7 of immediate. The condition needs 4 bits and the immediate field has 7, so THERE IS NO ROOM LEFT for a condition in a word that already has three registers in it. csel is therefore a DIFFERENT ENCODING, not an instruction with an extra field — which is the strongest form the argument can take, because it is arithmetic rather than a design preference.

One parsing note, because it is the kind of failure that prints like a result. The first version of that table matched the disassembly with a regex over the whole line, and its \s+ after the instruction word consumed the tab along with the padding — so the “mnemonic” it captured was the first operand. Nothing matched, the table came out empty, and the section that exists to prove that csel is an instruction rather than a name reported no instruction and no error. The section now says how many words it found, and it splits the line on its tab.