The Extension That Halves Instructions, and the One That Breaks Them

What the extension reserved, and what it did not

The method here is exhaustive and it is cheap. All 65,536 half-words, written into a .text section as data, disassembled by the second reader, and classified twice: once by this file’s reserved rules and once by whether the reader prints a mnemonic. A two-independent-classification check over an exhaustive set cannot be vacuous — a vacuous comparison of 49,152 items would have to compare nothing.

First the boundary, because it is the thing the plan got wrong, and the correction is worth stating plainly:

  CORRECTION TO THE PLAN, AND IT IS A BIG ONE.  The plan for this
  section said: "the number of reserved 16-bit patterns you can enumerate and
  verify against the assembler".  Measured, the answer is that the assembler
  REFUSES 16,384 of the 65,536 half-word patterns -- exactly a quarter,
  exactly bits[1:0] == 0b11 -- and it refuses them with the diagnostic

      instruction length does not match the encoding

  which is not a reservation message at all.  It is the assembler saying
  "that pattern is a 32-bit instruction, and you asked me for two bytes".
                

So there are two different questions and the plan conflated them:

• Of the 65,536 half-word patterns, 49,152 have bits[1:0] != 0b11 and are reachable as 16-bit instructions. 16,384 are not reachable at all, and that is a fact about the LENGTH RULE and not about the C extension. This is the number the assembler’s refusal is reporting, and reporting it as a reservation cost is how you end up claiming the extension gave up a quarter of the space.
• Of the 49,152 reachable ones, some are defined, some are HINTs, and some are RESERVED. That is the number the extension’s cost is made of, and it is 2,409.

$ python3 rvdec.py --space | sed -n '/quadrant   funct3/,/^$/p'
  quadrant   funct3   code points RESERVED  HINT rules here
  q0         000      8                     -
  q0         100      2048                  -
  q1         001      64                    -
  q1         011      32                    c.lui
  q1         100      128                   c.srli, c.srai
  q2         010      64                    -
  q2         011      64                    -
  q2         100      1                     c.mv, c.add
  TOTAL               2409
                

2,409 of 49,152, which is 4.90 per cent of the reachable compressed space. Read that against the quarter the assembler refuses and the plan’s framing is not merely wrong but misleading. And the distribution is the real finding: one cell — quadrant 0, funct3 = 100 — accounts for 2,048 of the 2,409, which is 85 per cent. The QUOTED reason is in the manual’s own opcode map, which prints two columns for the RV32 and RV64 variants and marks that cell Reserved in both. The cell held C.FLWSP in the RV32 draft; the RV64 column needed the slot for C.LD; and when the two columns were merged the cell was given up entirely. 2,048 code points — one twenty-fourth of the whole reachable compressed space — for one decision about one quadrant.

And five of the eight reserved cells are one-off rules that kill a cell because of a register value or an immediate value. All the same shape, and the shape is the point:

• C.ADDI4SPN with nzuimm = 0: 7 code points. An immediate of zero is reserved because the instruction ADDS something to sp, and adding zero is a different instruction. Not eight: the eighth, 0x0002, was given to C.SLLI64 by the RV128 work. One reserved code point is a code point somebody else claimed.
• C.ADDIW with rd = x0: 64. And in RV32 the same cell is C.JAL, which has no reserved code points. A reserved encoding in one base and a valid instruction in the other, at the same 16 bits — the C extension’s modularity showing up as a portability hazard.
• C.LUI with imm = 0: 32, and C.ADDI16SP with nzimm = 0 is the 33rd and dies with them, because the two share the cell and are told apart by the destination register.
• C.SUBW/C.ADDW’s reserved half: 128. Sixteen of the thirty-two (inst[12], bits[6:2]) combinations times eight registers, and the reserved ones are exactly the two funct2 values no base assigned.
• C.LWSP and C.LDSP with rd = x0: 64 each, not 32, because the CI format’s immediate is six bits and a zero register leaves all six free.
• And ONE code point, 0x8002 — rs1 = 0 with rs2 = 0, the single combination that C.JR, C.JALR, C.EBREAK, C.MV and C.ADD all reject. It is the only reserved compressed encoding a person is likely to meet in a hex dump, and it is reserved because five rules each exclude it. Its neighbour 0x9002 is C.EBREAK, one bit away, and a decoder that reads the cell without reading inst[12] reports a legal instruction as reserved.